This application claims priority under 35 U.S.C. xc2xa7119 from Korean Patent Application No. 2002-2509, filed on Jan. 16, 2002, the entirety of which is hereby incorporated by reference as if fully set forth herein.
1. Field of the Invention
The present invention relates to a semiconductor memory device and method for manufacturing the same, and more particularly, to a dynamic random access memory (DRAM) having a stack-shaped capacitor and a method for manufacturing the same.
2. Description of the Related Art
A dynamic random access memory (DRAM) among semiconductor memory devices is comprised of one transistor and one capacitor. Thus, in order to serve as a memory device, the DRAM must have sufficient capacitance. There is no problem when the design rule of the memory device is wide. However, as the memory device becomes highly integrated, its design rule becomes extremely dense and an area for each memory device becomes narrower, and thus, area per cell also decreases. A stack-shaped capacitor has been developed to obtain sufficient capacitance as the area becomes narrower. The stack-shaped capacitor can increase a surface area by forming an electrode with high depth even though the occupied area of the capacitor decreases. Thus the required capacitance of the capacitor can be obtained even though the design rule of the memory device becomes finer. However, in the stack-shaped capacitor, when the stack-shaped capacitor forms a storage node, a step between the cell area and a peripheral area becomes very severe. As a result, a metal interconnection process cannot be performed well due to an extreme pattern-thinning phenomenon caused by diffraction and irregular reflection of light, which is exposed due to a high step between a cell area and the peripheral area during a subsequent photolithographic process for metal interconnections in a case where a predetermined planarization process is not performed.
Thus, in a conventional planarization process between the cell area and the peripheral area, a very thick interlayer dielectric (ILD) film is formed on the surface of a semiconductor substrate after a capacitor process is completed. The cell area having a high step is opened after a predetermined photolithographic process, and then, the ILD film in the cell area is etched to a predetermined thickness through dry etching, and thereby removed. Then, the step between the cell area and the peripheral area is slightly decreased. The thick ILD film is again formed on the surface of the semiconductor substrate and is polished and removed and thereby planarized to enable the metal interconnection process on the entire surface of the semiconductor substrate through chemical mechanical polishing (CMP).
However, the photolithographic process for opening the cell area and a dry etching process is added to the conventional planarization process between the cell area and the peripheral area, and an additional planarization process using CMP is accompanied by a subsequent process, thus increasing the number of processes. Moreover, the photolithographic process and the CMP process are included, and thus the reliability of production is reduced, and the period of a manufacturing process becomes longer, and costs increase.
To solve the above problems, it is an object of the present invention to provide a semiconductor memory device and a method for manufacturing the same in which manufacturing processes are simplified, and a wide contact area is formed on a plate electrode for serving as the ground electrode of a capacitor so that a step between a cell area of a semiconductor chip and a peripheral area formed by a capacitor formed in the cell area is effectively decreased, thereby greatly reducing ground resistance, thus improving the electric characteristics of a memory device.
Accordingly, to achieve the above object, according to one embodiment, there is provided a semiconductor memory device. The semiconductor memory device includes an oxide layer for isolating individual devices which define device areas so that a cell area and a peripheral circuit area are separated from each other on a semiconductor substrate. The semiconductor memory device also includes: a plurality of MOS transistors, which are comprised of source areas, drain areas, and gates that are formed in the cell area and the peripheral circuit area; a bit line, which is formed on the plurality of MOS transistors and is electrically connected to the MOS transistors; a stack-shaped capacitor, which is comprised of a first electrode, a dielectric layer, and a second electrode between which the MOS transistors and the bit line in the cell area are interposed; a guard-ring pattern, which is interposed between the cell area and the peripheral circuit area; surrounds the cell area and is apart from the peripheral circuit area, and a contact fill for a plate electrode, which is formed in the guard-ring pattern and is in contact with the second electrode that is formed on the internal sidewall and the bottom of the guard-ring pattern.
The first electrode of the stack-shaped capacitor is electrically connected to the source areas and has a hollow cylindrical shape so that the area of a capacitor per area is increased, and capacitance is maximized. The first electrode is conductive polycrystalline silicon (polysilicon) such as an impurity-doped polycrystalline silicon, and further includes a barrier layer such as platinum (Pt), RuO, Rb, and RbO. The dielectric layer may be a combination layer of a silicon oxide layer and a silicon nitride layer, but is preferably formed of a high dielectric material that is at least one selected from Ta2O5, PZT, PZLT, BST, and Al2O3, such that the capacitance of the capacitor is increased for a given area.
The second electrode is formed in a block form to overlap a predetermined region adjacent to the peripheral circuit area including the entire cell area, and the second electrode is conductive polysilicon, such as an impurity-doped polysilicon, and the second electrode further includes a barrier layer, thereby preventing impurity atoms constituting a high dielectric layer from penetrating into junctions that are formed on a lower portion of the semiconductor memory device and thereby deteriorating electrical characteristics.
The guard-ring pattern is formed on the same surface as the bottom of the first electrode, and the second electrode is extended to the edge of the cell area on the bottom of the guard-ring pattern. At least a part of the contact fill for the plate electrode is electrically connected to the second electrode in the guard-ring pattern. The contact fill for the plate electrode includes a tungsten fill that is formed of tungsten in the center, and barrier metal that is formed outside of the tungsten fill adjacent to a recessed portion, thereby preventing the formation of fluoric components that penetrate into a lower MOS transistor from a tungsten (W) layer, which is a filling metal layer. The barrier metal is a combination layer of Ti and TiN.
To achieve the above object, according to another embodiment, there is provided a method for manufacturing a semiconductor memory device. A cell area is separated from a peripheral circuit area on a semiconductor substrate to form device active areas. A plurality of MOS transistors are formed in the device active areas of the cell area and the peripheral circuit area. A first interlayer dielectric (ILD) film is formed on the semiconductor substrate and a first electrode pattern and a guard-ring pattern surrounding the cell area are formed on the first ILD film. A conductive layer for a first electrode and an insulating layer for patterning are sequentially formed on the first electrode pattern and the guard-ring pattern. The entire cell area and a part of the guard-ring pattern are opened, and the conductive layer for the first electrode and the insulating layer for patterning are removed to the first ILD film, and a first electrode node in the cell area is formed. The insulating layer for patterning that is filled in the first electrode node is removed.
A dielectric layer and a conductive layer for a second electrode are formed on the semiconductor substrate. A pattern for the second electrode is formed on the conductive layer for the second electrode. A contact fill for a plate electrode is formed while being in contact with the second electrode that is formed on the sidewall and the bottom of the guard-ring pattern.
That is, in order to define the device active areas on the semiconductor substrate, the semiconductor substrate is partially recessed to a predetermined depth and forming a trench, and a silicon insulating layer is filled in the trench. Then, a gate insulating layer is formed on the device active areas, and a gate conductive layer is formed on the gate insulating layer. A mask insulating layer is formed on the gate conductive layer. In this case, preferably, the gate conductive layer is conductive polysilicon such as an impurity doped polysilicon or polycide, which is combined with metal silicide, thereby improving the conductivity of the gate. Then, a gate pattern is formed on a mask insulating layer and a gate conductive layer through a photolithographic process, and an insulating layer for a sidewall spacer is formed on the sidewall of the gate pattern, thereby completing a gate process. Then, source and drain junctions are formed by an ion implantation method using the gate as a mask. Here, the insulating layer for the sidewall spacer is a silicon nitride layer, thereby increasing dry etch selectivity with a silicon oxide layer when a self-aligned contact is formed. The source and drain areas form an N-type junction in the cell area, and form N-type and P-type junctions in the peripheral circuit area. A silicon insulating layer is formed, and a bit line conductive layer that is formed of polysilicon such as an impurity doped polysilicon and metal silicide, and a mask insulating layer for self-alignment that is formed of silicon nitride are formed on the silicon insulating layer. A bit line pattern is formed on the bit line conductive layer and the mask insulating layer for self-alignment, and then, an insulating layer spacer that is formed of silicon nitride is formed on the sidewall of the bit line pattern. In a case where the silicon insulating layer is formed, and the self-aligned contact is formed, the mask insulating layer and the insulating layer spacer that are formed of silicon nitride serve as a mask for dry etching.
A capacitor contact that is connected to the source area of the MOS transistor is formed to be electrically connected to the MOS transistor using a self-alignment method, and a capacitor contact pad is formed by filling a conductive layer in the capacitor contact. A first ILD film is thickly formed on the semiconductor substrate, and a photoresist is formed on the first ILD film.
A first electrode pattern is formed in the cell area in the photoresist and a band-shaped guard-ring pattern is formed in a boundary between the cell area and the peripheral circuit area while surrounding the cell area. In this case, the first ILD film includes a silicon nitride layer as an etch stopper in a lower portion of the first ILD film, and includes a silicon oxide layer that is formed on the etch stopper. As a result, another layer may be used as an etch stopper when a subsequent etching process having high selectivity is performed, and the silicon nitride layer, which is an etch stopper, is formed to be much thinner than the silicon oxide layer, thereby increasing the capacitor area after the silicon oxide layer is removed. Then, a first electrode pattern is formed in the cell area on the first ILD film through dry etching using the patterned photoresist as a mask, and a guard-ring pattern is formed in a boundary between the cell area and the peripheral circuit area while surrounding the cell area.
A conductive layer for a first electrode that is conductive polysilicon, such as an impurity doped polycrystalline silicon, and an insulating layer for patterning that is formed of silicon oxide by chemical vapor deposition (CVD) are sequentially formed in the first electrode pattern and the guard-ring pattern. Here, the insulating layer for patterning is formed in particular through plasma-enhanced CVD (PE CVD) using plasmas having a high deposition rate and a high etching rate in an etching solution. In this case, the conductive layer for the first electrode further includes a barrier layer that is one selected from TiN, RuO, Pt, Rb, and RbO, thereby preventing impurities that are contained in materials to be used later as a dielectric layer from into the MOS transistor and from deteriorating the electrical characteristics of the semiconductor memory device.
A photoresist is formed on the insulating layer for patterning, and a cell opening pattern is formed in the photoresist so that the peripheral circuit area is blocked and only the cell area is opened. The second insulating layer and the conductive layer for the first electrode are sequentially etched and removed through dry etching using the cell open pattern as a mask, thereby forming a first electrode node of the capacitor. The first electrode node is formed in the cell area, and the conductive layer for the first electrode is left in the peripheral circuit area, thereby protecting the first ILD film.
The insulating layer for patterning is wet etched and removed with an etching solution. Beneficially, the etching solution is a silicon oxide etchant containing hydrofluoric acid (HF) and buffered oxide etchant (BOE). As a result, the silicon nitride layer which composes the lower portion of the first ILD film is an etch stopper in the cell area, and polysilicon which composes the conductive layer for the first electrode is an etch stopper in the peripheral circuit area and the guard-ring pattern, thereby forming the first electrode node in the cell area, and the first ILD film that is formed of silicon oxide to the height of the first electrode is protected in the peripheral circuit area.
A dielectric layer is formed on the exposed surface of the first electrode node, and a conductive layer for a second electrode is formed on the dielectric layer so that the inside of the first electrode node is filled. In this case, the dielectric layer is formed of at least one selected from silicon nitride, silicon oxide, and a high dielectric material, and the high dielectric material is one selected from Ta2O5, Al2O3 and PZT, PLZT, and BST as perovskite-family ferroelectric materials. The conductive layer for the second electrode is conductive polysilicon, such as an impurity-doped polysilicon, and the conductive layer for the second electrode further includes a barrier layer, thereby preventing impurities from penetrating into a layer at an external side in a case where the dielectric layer is a high dielectric layer.
A photoresist is formed on the conductive layer for the second electrode, and a second electrode pattern having a block shape is formed in the photoresist so that a part of the second electrode pattern partially overlaps the peripheral circuit area including the cell area and the guard-ring pattern. The conductive layer for the second electrode, the dielectric layer and the conductive layer for the first electrode remaining in the peripheral circuit area are etched through dry etching using the patterned photoresist as a mask.
A second ILD film that is formed of silicon oxide through CVD is formed on the entire surface of the semiconductor substrate. A photoresist is formed on the second ILD film, and a contact pattern for a plate electrode having a block shape is formed in the photoresist to be larger than the actual size of an area where it overlaps the guard-ring pattern. The second ILD film in the guard-ring pattern is dry etched and completely removed by using the patterned photoresist as a mask, and a contact for the plate electrode is formed so that the sidewall and the bottom of the second electrode in the guard-ring pattern are completely exposed. Then, a contact filling conductive layer is formed of tungsten (W), and the contact filling conductive layer is removed evenly to the second ILD film, thereby forming a contact fill for the plate electrode. In this case, the contact filling conductive layer further includes Ti and TiN as a barrier layer.
In the semiconductor memory device and the method for manufacturing the same as disclosed herein, the guard-ring pattern is formed in a boundary between the cell area and the peripheral circuit area while surrounding the cell area, and thereby a step caused by manufacturing the stack-shaped capacitor is removed during a manufacturing process. In addition, the contact fill for the plate electrode is formed in the guard-ring pattern through a self-aligned contact method, and thereby the contact for the plate electrode is in direct contact with the bottom and the sidewall of the second electrode as a ground electrode. Thus, the contact area is increased greatly, the contact resistance is substantially reduced, and the electrical characteristics of the memory device are more stabilized.